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Layout engineer

UST Global

This is a Full-time position in Cupertino, CA posted December 12, 2019.

· Experience in analog and/or mixed-signal layout design of deep sub-micron CMOS circuits
· Experience implementing analog blocks such as OP-AMPs, PLLs, ADCs, DACs, Bandgap, LDO, Voltage Regulator, Sense Amps, or Memory layouts
· Strong hands on experience in custom and standard cell-based floor-planning and hierarchical layout assembly
· Hands on and deep understanding of layout techniques for handling IR drop, RC delay, electro-migration, self-heating and coupling capacitance, experience in block level floor planning, understanding the design rules, Device matching, minimization of parasitic.

· Experienced in interpreting Calibre DRC, ERC, LVS reports
· Knowledge of Cadence layout tools
· Knowledge of skill code and layout automation is a plus
· Excellent communication skills and ability to work with cross-functional teams